In general, an operation of the CAM includes a write operation for writing a storage data, a read operation for retrieving the storage data and a retrieve operation for detecting a consistency between a retrieval data and the storage data. In the retrieve operation, the consistency between the retrieval data and the storage data is simultaneously detected in all bits, and a result of the retrieve operation at each address is outputted.
A conventional CAM memory cell 100 shown in FIG. 10 comprises a memory unit 101 for storing data and a data compare unit 102 for detecting the consistency between the data stored in the memory unit 101 and a retrieval data inputted from outside of the CAM. A compare line CP and an anti-compare line /CP for inputting a retrieval data are connected to the data compare unit 102.
In the write operation, a word line WL at a write address is rendered “H” so that transistors 103 and 104 are turned on. Then, a write data in a bit line BL and a reversal data in an anti-bit line /BL are stored in inverters 105 and 106.
In the retrieve operation, a transistor 110 is turned on so that a match line MT is pre-charged, and a value of the compare line CP and a value of the anti-compare line /CP as a reversal data thereof are compared to each other in the data compare unit 102. The match line MT retains the “H” level when the compared values are consistent with each other, while the “H” level turns to an “L” level when they are inconsistent.
For example, when the storage data shows “1”, an output of the inverter 106 is at the “H” level and an output of the inverter 105 is at the “L” level, and transistors 107 and 108 corresponding to the respective inverters are turned on and off respectively. When “1” is supplied to the compare line CP and “0” is supplied to the anti-compare line /CP in the foregoing conditions, a transistor 109 retains the OFF state, and the pre-charged match line MT retains the “H” level. In other words, the match line MT is at the “H” level because the storage data and the retrieval data both show the value “1” and are, therefore, consistent with each other.
On the contrary to the foregoing description, when “0” is supplied to the compare line CP and “1” is supplied to the anti-compare line /CP, the transistor 109 is in the ON state, and the match line MT is at the “L” level. In other words, the match line MT turns to the “L” level because the storage data shows “1” and the retrieval data shows “0” and are, therefore, inconsistent with each other.
Further, some of the CAMs have a mask function. FIG. 11 shows a diagram of a memory cell of a conventional CAM provided with the mask function. A data compare unit 203 is interposed between a memory unit 201 and a mask memory cell 202. A transistor 204 in the data compare unit 203 corresponds to the transistor 109 shown in FIG. 10. A source of a transistor 205 connected to the mask memory cell 202 in the data compare unit 203 is connected to a drain of the transistor 204.
When “0” is stored in the mask memory cell 202 here, the transistor 205 is turned on, and the data compare unit 203 operates in the same manner as shown in FIG. 10. When “1” is stored in the mask memory cell 202, the transistor 205 is turned off, which renders the transistor 204 inactive. Accordingly, the match line MT turns to the “H” level irrespective of a state of the memory unit 201.
FIG. 12 is a timing chart of the write operation of the CAM, and FIG. 13 is a timing chart of the retrieve operation of the CAM.
Given that the write operation and the retrieve operation are both instructed based on an identical clock cycle in a conventional structure of a circuit as shown in FIG. 14, there is an inconvenience that an output of the match line becomes uncertain because an indefinite data that is currently written and not finally determined in the memory unit is compared to the retrieval data. In order to avoid the inconvenience, it is necessary to prohibit the execution of both the write and retrieve operations based on the identical clock cycle, however, it reduces an efficiency of the retrieve operation.